This relates to integrated circuits and, more particularly, to generating reset sequences for registers within an integrated circuit design.
Every transition from one technology node to the nest has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit area on an integrated circuit die. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which have led to performance increases.
To further increase the performance, solutions such as register retiming have been proposed, where registers are moved among portions of combinational logic, thereby achieving a more balanced distribution of delays between registers, and thus the integrated circuit may be operated at a potentially higher clock frequency.
The registers are typically implemented using clock-edge-triggered flip-flops. Prior to retiming, when the integrated circuit is powered up, these digital flip-flops are also powered to an initial state, but this initial state may be unknown. Therefore, a reset sequence is typically provided to the flip-flops to reset the flip-flops and bring them to a known reset state.
However, after retiming, the retimed integrated circuit may behave differently from the integrated circuit prior to retiming. In some cases, the same reset sequence provided to the flip-flops prior to retiming will not work with the retimed flip-flops. Therefore, it would be desirable to account for flip-flops moved during retiming and to provide an updated reset sequence for the retimed flip-flops.
It is within this context that the embodiments herein arise.